1. Field of the Invention
The present invention relates to a display driving circuit, and more particularly, to a display driving circuit which uses an amplifier, appropriate for a display driving circuit, as a buffer.
2. Description of the Related Art
A display driving circuit functions to output valid data having image information to be reproduced, to a display panel.
FIG. 1 illustrates an output section of a display driving circuit.
Referring to FIG. 1, an output section of a display driving circuit 100 includes a positive gamma reference voltage generating circuit 110, a negative gamma reference voltage generating circuit 120, a digital circuit 130, a path transistor logic block 140, a path selecting switch circuit 150, a buffer block 160, an output selecting switch circuit 170, and an electric charge sharing switch circuit 180.
The path transistor logic block 140 selects and outputs gamma reference voltages corresponding to N-bit digital data outputted from the digital circuit 130, among 2N (N is an integer) number of gamma reference voltages outputted from each of the positive gamma reference voltage generating circuit 110 and the negative gamma reference voltage generating circuit 120. The plurality of selected gamma reference voltages are outputted to one path of a first path as a direct path and a second path as a cross path by the path selecting switch circuit 150. The first path as a direct path means a path in which switches to be turned on by a first path selecting signal P1 are arranged, and the second path as a cross path means a path in which switches to be turned on by a second path selecting signal P1B are arranged. After being buffered in the buffer block 160, the gamma reference voltages outputted from the path selecting switch circuit 150 are transmitted to a display panel (not shown) via output terminals CH(1) through CH(M) (M is an integer) for a time during which an output selecting signal P3 is activated in the output selecting switch circuit 170. The electric charge sharing switch circuit 180 short-circuits the output terminals CH(1) through CH(M) for a predetermined time during which an electric charge sharing signal P2 is activated, so that all the output terminals CH(1) through CH(M) can share their electric charges.
Since the display driving circuit is generally known in the art, component elements, connection relationships among them, and their operational characteristics will not be described herein.
FIG. 2 is an internal circuit diagram of a plurality of amplifiers ARR used as buffers in the buffer block 160 shown in FIG. 1.
Referring to FIG. 2, an amplifier 200 includes an input stage 210, a bias stage 220, and an output stage 230.
The input stage 210 receives a positive input signal INP and a negative input signal INN by two P-type MOS transistors and two N-type MOS transistors in order to increase a common mode input voltage range. That is to say, the positive input signal INP is received by a P-type input MOS transistor P2 and an N-type input MOS transistor N2, and the negative input signal INN is received by a P-type input MOS transistor P1 and an N-type input MOS transistor N1. The common terminal of the two P-type input MOS transistors P1 and P2 is connected to a P-type current source P3, and the other remaining terminals thereof are connected to the bias stage 220. The common terminal of the two N-type input MOS transistors N1 and N2 is connected to an N-type current source N3, and the other remaining terminals thereof are connected to the bias stage 220.
The bias stage generates two class AB output signals V1 and V2 which correspond to the difference between the positive input signal INP and the negative input signal INN. The output stage 230 generates an output signal VOUT in response to the two class AB output signals V1 and V2.
In general, a method for manufacturing a semiconductor include a process for implanting impurities into a substrate using a mask formed with a preselected pattern, a process for diffusing the implanted impurities, a process for depositing a substance, and a process for etching the deposited substance to have a predefined pattern. In this regard, actually realized circuit elements cannot but have some differences from designed values due to non-correspondence of a mask pattern to a designed value caused in the course of fabricating the mask, non-correspondence and non-uniformity of an amount of impurities implanted into the substrate, and an etching tolerance.
The amplifier 200 shown in FIG. 2 is realized using twenty MOS transistors. These MOS transistors are designed to operate in a saturation region. The operational characteristics of MOS transistors are determined by the threshold voltages, the lengths of gate areas, the widths of the gate areas, and the material and the thickness of gate insulators. The threshold voltages, the lengths of gate areas, and the widths of the gate areas actually become slightly different from designed values due to the above-described reasons. Changes in the operational characteristics of the MOS transistors are usually represented as an offset voltage in an amplifier.
FIG. 3 shows offset spread in the conventional amplifier.
Referring to FIG. 3, an offset voltage becomes low or high with respect to an expected value due to the non-correspondence between a designed value and an actually realized transistor.
In order to reduce the influence of the offset, a method has been proposed in the art in which MOS transistors constituting an amplifier circuit are arranged to have a symmetric structure, and symmetric MOS transistors are alternately used using dithering switches.
FIG. 4 is a circuit diagram illustrating an amplifier added with dithering switches.
Referring to FIG. 4, an amplifier 400 added with dithering switches minimizes the offset by way of operation of the dithering switches which alternately switch symmetric MOS transistors and current mirrors. The dithering switches are switched in response to two signals A and B which are alternately enabled. Since the amplifier 400 added with the dithering switches are known in the art through papers, etc., description of the connection relationship and operation of the amplifier 400 will be omitted herein.
In the case of the amplifier 400 shown in FIG. 4, although the offset is minimized, because the amplifier 400 has twenty MOS transistors and ten dithering switches, a disadvantage is caused in that the area occupied by the amplifier 400 in a layout markedly increases. In particular, while the area occupied by the switches is not so great, the area occupied by the twenty MOS transistors in the layout is considerably great.